This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-119981, filed Apr. 20, 2000, the entire contents of which are incorporated herein by reference.
This invention relates to a multichip semiconductor memory device and memory card and more particularly to a multichip semiconductor device and memory card on which a plurality of semiconductor chips or a plurality of semiconductor chips having semiconductor memories and logic circuits formed therein are mounted in a stacked form.
Recently, memory cards are widely used as film media of digital cameras and storage devices of mobile personal computers. For example, as the memory card, an SSFDC (Solid-State Floppy Disk Card) having a NAND-type E2PROM which is a nonvolatile memory mounted thereon or a so-called xe2x80x9cSmart Mediaxe2x80x9d is known. At present, large-capacity memory cards each having one or two 64-Mbit NAND-type E2PROMs mounted thereon are commercially available. However, recently, a new market for multimedia or the like has opened up, a demand for larger-capacity memory elements has arisen and it is strongly desired to realize a larger memory capacity.
As one technique for realizing a large-capacity memory device, a technique for forming semiconductor chips each having connection plugs which are called chip through plugs and provided in through holes formed to penetrate through the semiconductor substrate and forming a multichip semiconductor device by mounting a plurality of semiconductor chips in a stacked form is known. Various control signals and data items are supplied to the plurality of stacked semiconductor chips from the mounting board via the chip through plugs or data items are read out therefrom. However, the technique has inherent problems that need to be solved.
For example, in the conventional on-plane-board mounting technique, it is possible to distribute four chip control signals (chip enable bars) when a memory device is constructed by use of four semiconductor memory chips with the same structure. However, if the semiconductor chips are stacked in order to reduce the mounting area, it becomes necessary to divide the chip control signal inside the respective chips. This means that four different types of chips are manufactured and is not advisable when taking the manufacturing cost into consideration.
Before the present invention is made, one of the inventors hereof and three other persons proposed a multichip semiconductor device that comprises a plurality of semiconductor chips each having elements integrated in the semiconductor substrate, as is disclosed in Japanese Patent Application No. 10-213880 (corresponding U.S. patent application Ser. No. 09/363,031 which matured into a patent on Jan. 17, 2001). The multichip semiconductor device is formed by stacking a plurality of semiconductor chips of substantially the same structure, each having connection plugs in through holes made in the semiconductor substrate. In each semiconductor chip, bumps connect some of the connection plugs. Each semiconductor chip has optional circuits, at least one of which is selected in accordance with which connection plugs are connected by the bumps.
According to the multichip semiconductor device with the above construction, it is possible to individually supply chip control signals to the chips even if the chips with the same structure are used by respectively forming the optional circuits in the plurality of chips and selectively forming the bumps used for connection with the plugs for the respective chips.
However, when the above method is used, it is required to selectively connect the bumps to the plugs, and if the bumps are formed by use of a solder-plating method, it is required to form a mask for each chip. Further, if the bumps are simultaneously formed for each chip as in a transfer bump method, the setting position of the bumps must be changed for each stacked stage of the chip, and therefore, it is required to replace the mask at the time of formation of the bumps or it is required to provide devices for the respective stacked stages. In a case where bumps are simultaneously formed on each wafer, for example, where bumps are formed by plating on the wafer, it is required to form bumps in different positions for each stacked stage and the compatibility of the respective stacked layers is not allowed.
Thus, the technique disclosed in the prior application can individually supply chip control signals and lower the manufacturing cost even if the chips with the same structure are stacked, but it can be still improved in the respect that the production efficiency is further enhanced and the manufacturing cost is further lowered.
As described above, in the conventional multichip semiconductor device and memory card, it is possible to individually supply chip control signals and lower the manufacturing cost even if the chips with the same structure are stacked, but they are still improved in the respect that the production efficiency is further enhanced and the manufacturing cost is further lowered.
According to an aspect of the present invention, there is provided a multichip semiconductor device having a plurality of semiconductor chips, each of the plurality of semiconductor chips comprising a semiconductor substrate having elements integrated therein, connection plugs formed in through holes formed to penetrate through the semiconductor substrate, and fuse portions provided between connection plugs and corresponding bumps, wherein the plurality of semiconductor chips are stacked and mounted by connecting the connection plugs of the respective semiconductor chips via the bumps.
According to another aspect of the present invention, there is provided a memory card comprising a plurality of semiconductor memory chips with substantially the same structure, each including connection plugs formed in through holes formed to penetrate through a semiconductor substrate, and fuse portions respectively provided between the connection plugs and corresponding bump forming areas and being selectively cut off for specifying assignment of an address, bumps formed in substantially the same pattern, for connecting the connection plugs of the semiconductor memory chips, a card-form package for sealing the plurality of semiconductor memory chips in a stacked form, and terminals provided in the card-form package, for transferring signals with respect to the semiconductor memory chips via the connection plugs, fuse portions and bumps.
According to still another aspect of the present invention, there is provided multichip semiconductor device having a plurality of semiconductor chips stacked one upon another, each of which comprises a semiconductor substrate having elements integrated therein, a chip through plug provided in the semiconductor substrate, for receiving a chip address, and a chip-identifying circuit provided in the semiconductor substrate, for receiving the chip address from the chip through plug and determining from the chip address how many other chips are located below the semiconductor chip, wherein the chip identifying circuit of each semiconductor chip processes the chip address and then outputs the chip address to the chip-through plug of the immediately upper chip.